For a considerable time, computer program developers and users have been able to benefit from advances in technology that have shrunk silicon feature sizes. As the size of the devices (e.g., microprocessors and memory) that can be created grows smaller, the devices become faster, cheaper and more densely packed. The effect of these advances has allowed contemporary computing to continue to use a control driven (Von Neumann) execution model, in which a series of instructions is written by a programmer for the processor to follow, and when executed in order, will perform a desired computation.
However, the limits of such conventional computing technology are being reached. This is because of a number of problems that arise as the silicon feature size continues to shrink. For example, effects such as crosstalk, capacitive loading, defect density and heat dissipation become more pronounced as the chips become more densely packed.
As a result, in an attempt to continue to advance computational power, manufacturers are introducing solutions based on some amount of parallel computing. For example, modern processors automatically attempt to extract some parallelism from control driven code, by attempting to find operations that can be executed in any order, and thus can be executed in parallel, without changing the outcome. However, extracting parallelism in this way is a complex problem that is not particularly successful or efficient, as it requires a significant amount of looking ahead or behind in the instructions to determine which operations, if any, can be conducted in parallel. Despite such complexities, the computer industry is moving towards parallel computing. What is needed is a better architecture for parallel computing.